Early assessment of leakage power for system level design

Author

Talarico, C. ; Pillilli, B. ; Vakati, K.L. ; Wang, J.M.

Author_Institution

Dept. of Electr. & Comput. Eng., Arizona Univ., Tucson, AZ, USA

fYear

2005

fDate

21-23 March 2005

Firstpage

133

Lastpage

136

Abstract

This paper presents a system level methodology for analyzing leakage power in the early stages of a system design. The assessment of leakage takes into account the simultaneous effect of threshold-voltage (Vt), oxide thickness (t_ox), device width (W), the inputs applied and statistical process variations. The approach has been validated by applying it to the design of a digital signal processing system. The results indicate that our power estimation technique is within 10% of SPICE, with the benefit of executing 15× faster.

Keywords

CMOS integrated circuits; digital signal processing chips; integrated circuit design; leakage currents; power consumption; device width; digital signal processing system; leakage power; oxide thickness; power estimation; statistical process variations; system level design; threshold voltage; Design engineering; Energy consumption; Equations; Integrated circuit technology; Polynomials; Power engineering and energy; Power engineering computing; Signal design; Stochastic processes; System-level design;

fLanguage

English

Publisher

ieee

Conference_Titel

Quality of Electronic Design, 2005. ISQED 2005. Sixth International Symposium on

Print_ISBN

0-7695-2301-3

Type

conf

DOI

10.1109/ISQED.2005.50

Filename

1410571