Title :
Buffer planning algorithm based on partial clustered floorplanning
Author :
Ma, Yuchun ; Hong, Xianlong ; Dong, Sheqin ; Chen, Song ; Cheng, Chung-Kuan
Author_Institution :
Dept. of Comput. Sci. & Technol., Tsinghua Univ., Beijing, China
Abstract :
In this paper, we propose a partial clustered floorplanning methodology with buffer planning. The theoretic analyses show that the timing constraints can be transferred into bounding box constraint and the spacing between buffers is somewhat stable. Therefore the critical nets can be controlled by the clustering strategy. The cluster strategies in our approach are designed not only for localizing the critical nets, but also for facilitating the buffer insertion of long wires. Based on the CBL representation, we devise sub CBL to represent the cluster and embed the optimization of the clusters into the annealing process. In most of the previous clustering-based methods, the shape of the cluster was restricted to a square. In this paper, however, we remove this restriction by treating the cluster as the sub packing. Our method can achieve a very stable performance. Experimental results on the MCNC benchmark show the effectiveness of the method and prove the correctness of the theoretic analyses.
Keywords :
annealing; buffer circuits; integrated circuit layout; timing; CBL representation; MCNC benchmark; annealing process; bounding box constraint; buffer insertion; buffer planning; critical nets; partial clustered floorplanning; stable performance; sub packing; timing constraints; Annealing; Circuits; Clustering algorithms; Computer science; Constraint theory; Delay; Shape; Technology planning; Timing; Wires;
Conference_Titel :
Quality of Electronic Design, 2005. ISQED 2005. Sixth International Symposium on
Print_ISBN :
0-7695-2301-3
DOI :
10.1109/ISQED.2005.27