DocumentCode
430243
Title
IP quality: a design, not a verification problem
Author
Keating, Michael
fYear
2005
fDate
21-23 March 2005
Firstpage
220
Lastpage
224
Abstract
Last year at ISQED, the author presented a paper describing the challenge IP providers face: customers demand zero-defect IP, yet this is beyond state of the art. This paper presents a possible path to address some of the key limiting issues described last year. Starting with an argument that verification cannot address the IP quality challenge, the paper argues that design methodology changes are the most likely path to increasing IP quality. It describes methods for measuring and reducing the state space of designs, and for representing the state space in a way that leads to more effective reasoning about the design. Finally, it discusses some recent experiments with formal and informal specification.
Keywords
formal verification; hardware-software codesign; industrial property; state-space methods; IP quality; formal specification; informal specification; reasoning; state space representation; zero-defect IP; Application software; Computer bugs; Design methodology; Hardware; Space technology; State-space methods; Testing; Universal Serial Bus;
fLanguage
English
Publisher
ieee
Conference_Titel
Quality of Electronic Design, 2005. ISQED 2005. Sixth International Symposium on
Print_ISBN
0-7695-2301-3
Type
conf
DOI
10.1109/ISQED.2005.69
Filename
1410587
Link To Document