DocumentCode
430247
Title
Parallel Processing using Data Localization for MPEG2 Encoding on OSCAR Chip Multiprocessor
Author
Kodaka, Takeshi ; Nakano, Hirofumi ; Kimura, Keiji ; Kasahara, Hironori
Author_Institution
Dept. of Comput. Sci., Waseda Univ.
fYear
2004
fDate
12-14 Jan. 2004
Firstpage
119
Lastpage
127
Abstract
Currently, many people are enjoying multimedia applications with image and audio processing on PCs, PDAs, mobile phones and so on. With the popularization of the multimedia applications, needs for low cost, low power consumption and high performance processors has been increasing. To this end, chip multiprocessor architectures which allow us to attain scalable performance improvement by using multigrain parallelism are attracting much attention. However, in order to extract higher performance on a chip multiprocessor, more sophisticated software techniques are required, such as decomposing a program into adequate grain of tasks, assigning them onto processors considering parallelism, data locality optimization and so on. This paper describes a parallel processing scheme for MPEG2 encoding using data localization which improve execution efficiency assigning coarse grain tasks sharing same data on a same processor consecutively for a chip multiprocessor. The performance evaluation on OSCAR chip multiprocessor architecture shows that proposed scheme gives us 6.97 times speedup using 8 processors and 10.93 times speedup using 16 processors against sequential execution time respectively. Moreover, the proposed scheme gives us 1.61 times speedup using 8 processors and 2.08 times speedup using 16 processors against loop parallel processing which has been widely used for multiprocessor systems using the same number of processors
Keywords
low-power electronics; microprocessor chips; multimedia computing; multiprocessing systems; parallel processing; video coding; MPEG2 encoding; OSCAR chip multiprocessor; PC; PDA; audio processing; chip multiprocessor architectures; data locality optimization; data localization; image processing; low power consumption; mobile phones; multigrain parallelism; multimedia applications; parallel processing; software techniques; Application software; Computer architecture; Costs; Data mining; Encoding; Energy consumption; Mobile handsets; Parallel processing; Personal communication networks; Personal digital assistants;
fLanguage
English
Publisher
ieee
Conference_Titel
Innovative Architecture for Future Generation High-Performance Processors and Systems, 2004. Proceedings
Conference_Location
Maui, HI
ISSN
1537-3223
Print_ISBN
0-7695-2205-X
Type
conf
DOI
10.1109/IWIA.2004.10021
Filename
1410687
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