DocumentCode
430270
Title
Reconfigurable IP blocks: a survey [SoC]
Author
Nurmi, Jari
fYear
2004
fDate
16-18 Nov. 2004
Firstpage
117
Lastpage
122
Abstract
An extensive survey concentrating totally on reconfigurable IP blocks is given. The most remarkable prevailing implementations are categorized according to the computational granularity, communication topology and source of block, i.e. academic vs. commercial. Also our own research results in this field are included in the classification.
Keywords
circuit CAD; field programmable gate arrays; industrial property; integrated circuit design; logic CAD; reconfigurable architectures; system-on-chip; FPGA; IP block source; SoC; communication topology; computational granularity; prevailing implementations; reconfigurable IP blocks; system-on-chip; Character generation; Field programmable gate arrays; Hardware; Intellectual property; Large scale integration; Manufacturing processes; Silicon; Table lookup; Topology; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
System-on-Chip, 2004. Proceedings. 2004 International Symposium on
Print_ISBN
0-7803-8558-6
Type
conf
DOI
10.1109/ISSOC.2004.1411163
Filename
1411163
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