Low-voltage pipelined ADC using class-AB pseudo-differential OTA

Author

Chaloenlarp, W. ; Thanachayanont, A.

Author_Institution

Dept. of Electron. Eng., King Mongkut´´s Inst. of Technol., Bangkok, Thailand

Volume

1

fYear

2004

fDate

26-29 Oct. 2004

Firstpage

128

Abstract

This paper describes the design of a low-voltage low-power pipelined analog-to-digital converter using a new class-AB pseudo-differential operational transconductance amplifier (OTA). The class-AB OTA employed in this work makes use of partial positive feedback to enhance its transconductance, which allows large gain-bandwidth product with low power dissipation. A 6 bit 15.36 MS/s pipelined ADC has been designed using a 0.35 μm CMOS process. Simulation results show that the ADC can achieve a maximum DNL and INL of 0.5 LSB and 0.59 LSB, respectively, and an SFDR of 47.5 dB, while draining 2.8 mA from a 2 V supply voltage.

Keywords

3G mobile communication; CMOS integrated circuits; analogue-digital conversion; circuit simulation; code division multiple access; integrated circuit design; integrated circuit modelling; low-power electronics; operational amplifiers; pipeline processing; radio receivers; 0.35 micron; 2 V; 2.8 mA; 3G WCDMA receiver; 6 bit; CMOS process; DNL; INL; SFDR; class-AB pseudo-differential OTA; class-AB pseudo-differential operational transconductance amplifier; gain-bandwidth product; low-power pipelined analog-to-digital converter design; low-voltage pipelined ADC; partial positive feedback; pipelined ADC; power dissipation; supply voltage; Capacitors; Circuits; Delay; Design engineering; Energy consumption; Frequency; Multiaccess communication; Power dissipation; Transconductance; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Communications and Information Technology, 2004. ISCIT 2004. IEEE International Symposium on

Print_ISBN

0-7803-8593-4

Type

conf

DOI

10.1109/ISCIT.2004.1412464

Filename

1412464