Low-voltage pipelined ADC using class-AB pseudo-differential OTA

This paper describes the design of a low-voltage low-power pipelined analog-to-digital converter using a new class-AB pseudo-differential operational transconductance amplifier (OTA). The class-AB OTA employed in this work makes use of partial positive feedback to enhance its transconductance, which allows large gain-bandwidth product with low power dissipation. A 6 bit 15.36 MS/s pipelined ADC has been designed using a 0.35 μm CMOS process. Simulation results show that the ADC can achieve a maximum DNL and INL of 0.5 LSB and 0.59 LSB, respectively, and an SFDR of 47.5 dB, while draining 2.8 mA from a 2 V supply voltage.