A speech codec with a class AB switch-current sigma-delta modulator and an area-efficient decimator/interpolator

A speech codec including four main blocks, a class AB switched-current sigma-delta modulator (SDM), a decimator, an interpolator, and a sigma-delta demodulator (SDDM) is presented. In order to achieve low-power consumption and wide dynamic range, a novel class AB switched-current (SI) integrator is adopted to implement the SDM with over-sampling ratio (OSR) of 64. In addition, design of a reduced-multiplier structure is proposed and applied to the finite impulse response (FIR) filters of the decimator and the interpolator which both of them share the most of hardware in the implementation. Therefore, the number of multipliers and the chip area are reduced. The speech codec was implemented using the TSMC 0.35μm 2P4M standard CMOS process technology. Simulation results with an input of 1kHz sinusoidal wave in the 4 kHz bandwidth show that the speech codec has a maximum signal-to-noise and distortion ratio (SNDR) of 46dB and dynamic range over 65dB with a single 2.5V supply voltage.