A multithreaded HDL simulator for deep submicron SoC designs

Author

Chan, Terence

Author_Institution

TJ Syst., Dublin, CA, USA

Volume

1

fYear

2004

fDate

6-9 Dec. 2004

Firstpage

77

Abstract

This work describes a multithreaded, 64-bit, HDL (hardware description language) simulator, V2Sim™, which can significantly accelerate the design verification of advanced deep submicron system-on-chip (SoC) circuits by 10× or more on any commercial symmetrical multiprocessing (SMP) computers. This work presents the patented, multithreaded simulation algorithm used by V2Sim™, and benchmark results of V2Sim™ will be depicted to demonstrate the effectiveness of the state-of-the-art algorithm.

Keywords

circuit simulation; formal verification; hardware description languages; integrated circuit design; multi-threading; multiprocessing systems; system-on-chip; V2Sim; deep submicron SoC designs; design verification; hardware description language; multithreaded HDL simulator; multithreaded simulation algorithm; symmetrical multiprocessing computers; system-on-chip circuits; Central Processing Unit; Circuit simulation; Computational modeling; Hardware design languages; Integrated circuit technology; Logic design; Operating systems; Time to market; Timing; Yarn;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2004. Proceedings. The 2004 IEEE Asia-Pacific Conference on

Print_ISBN

0-7803-8660-4

Type

conf

DOI

10.1109/APCCAS.2004.1412695

Filename

1412695