Efficient DSP architecture for Viterbi decoding with small trace back latency

This work proposes specialized DSP instructions and their hardware architecture for the Viterbi algorithm. The proposed architecture can reduce the trace back (TB) latency and can support various wireless communication standards. The proposed instructions perform the add compare select (ACS) and TB operations in parallel and the architecture has special hardware, called the offset calculation unit (OCU), which automatically calculates data addresses for acceleration of the trellis butterfly computations. When the constraint length K is 5, the proposed architecture can reduce the decoding cycles up to about 17% compared with Carmel DSP and about 45% compared with TMS320C55x.