DocumentCode :
430662
Title :
Experimental evaluations of high-level energy optimization based on thread partitioning
Author :
Uchida, Jumpei ; Myaoka, Yuichim ; Togawa, Nozomu ; Yanagisawa, Musao ; Ohtsuk, Totsuo
Author_Institution :
Dept. of Comput. Sci., Waseda Univ., Tokyo, Japan
Volume :
1
fYear :
2004
fDate :
6-9 Dec. 2004
Firstpage :
161
Abstract :
This work presents a thread partitioning algorithm for high-level synthesis systems which generate low energy circuits. In the algorithm, we partition a thread into two sub-threads, one of which has RF and the other does not have RF. The partitioned sub-threads need to be synchronized with each other to keep the data dependency of the original thread. Since the partitioned sub-threads have waiting time for synchronization, gated clocks can be applied to each sub-thread. We achieve 33% energy reduction when we apply our proposed algorithm to a JPEG encoder.
Keywords :
circuit optimisation; high level synthesis; logic partitioning; JPEG encoder; data dependency; gated clocks; high-level energy optimization; high-level synthesis; low energy circuits; thread partitioning; Circuit synthesis; Clocks; Computer science; Delay estimation; Energy consumption; Partitioning algorithms; Radio frequency; Registers; Synchronization; Yarn;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems, 2004. Proceedings. The 2004 IEEE Asia-Pacific Conference on
Print_ISBN :
0-7803-8660-4
Type :
conf
DOI :
10.1109/APCCAS.2004.1412717
Filename :
1412717
Link To Document :
بازگشت