• DocumentCode
    430691
  • Title

    An ultra low-power output feedback flip-flop

  • Author

    Phyu, Myint Wai ; Goh, Wang Ling ; Yeo, Kiaf Seng

  • Author_Institution
    Centre for Integrated Circuits & Syst., Nanyang Technol. Univ.
  • Volume
    1
  • fYear
    2004
  • fDate
    6-9 Dec. 2004
  • Firstpage
    341
  • Abstract
    In this paper, we proposed a new low-power output feedback single edge-triggered flip-flop (FBFF) that eliminates unnecessary internal transitions at the precharge node. As a result, the proposed FBFF is able to achieve substantial power reduction with no impact on its latency. The comparison of simulation results had indicated a maximum power saving of 87.9% during low input activities and an enhanced power-delay-product (in terms of the clock-to-output delay) of 8%-50%
  • Keywords
    circuit feedback; flip-flops; low-power electronics; timing circuits; FBFF; feedback single edge-triggered flip-flop; internal transition; output feedback flip-flop; power delay product; power reduction; power saving; precharge node; Circuit simulation; Clocks; Delay; Digital systems; Energy consumption; Flip-flops; Inverters; Latches; Output feedback; Power dissipation;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems, 2004. Proceedings. The 2004 IEEE Asia-Pacific Conference on
  • Conference_Location
    Tainan
  • Print_ISBN
    0-7803-8660-4
  • Type

    conf

  • DOI
    10.1109/APCCAS.2004.1412765
  • Filename
    1412765
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=430691