Title :
0.75-V subthreshold CMOS logic using dynamic substrate bias
Author :
Hung, Yu-Cherng ; Liu, Bin-Da
Author_Institution :
Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan
Abstract :
In this paper, a 0.75-V CMOS logic operated in sub threshold region is proposed. Based on dynamic substrate bias, the supply voltage of the circuit is effectively reduced. Using UMC 0.5-mum CMOS technology, the logic circuits are verified by inverter function, NOR gate, exclusive OR gate, full adder, and ring oscillator. Including I/O pad capacitance, the results of the chip measurement show that the response time of this circuit is order of 100 mus under 0.75-V supply
Keywords :
CMOS logic circuits; adders; capacitance measurement; logic gates; oscillators; substrates; 0.5 micron; 0.75 V; CMOS logic circuit; I/O pad capacitance; NOR gate; OR gate; adder; chip measurement; dynamic substrate bias; inverter function; ring oscillator; sub threshold region; supply voltage; Adders; CMOS logic circuits; CMOS technology; Capacitance measurement; Inverters; Logic circuits; Ring oscillators; Semiconductor device measurement; Time measurement; Voltage;
Conference_Titel :
Circuits and Systems, 2004. Proceedings. The 2004 IEEE Asia-Pacific Conference on
Conference_Location :
Tainan
Print_ISBN :
0-7803-8660-4
DOI :
10.1109/APCCAS.2004.1412766
