Two efficient area reduction methods for implementations of the Rijndael advanced encryption standard

Author

Hsiao, Shen-Fu ; Chen, Ming-Chih

Author_Institution

Dept. of Comput. Sci. & Eng., Nat. Sun-Yat Sen Univ., Kaohsiung

Volume

1

fYear

2004

fDate

6-9 Dec. 2004

Firstpage

353

Abstract

In this paper, we propose two methods to reduce the area cost of AES chip. The first method combines the SubBytes(), ShiftRows() and MixColumns() transformations in the cipher process, and the InvMixColumns(), InvShiftRows() and InvSubBytes() in the decipher process through the bit-level substitution and minimization. The second method integrates the combined SubBytes()/ShiftRows()/MixColumns() with the InvMixColumns()/InvShiftRows()/InvSubBytes() into a single function unit by sharing the common operations. Experimental results show that our design saves 21 % area cost of the entire AES chip

Keywords

cryptography; microprocessor chips; minimisation; standards; AES chip; InvMixColumns; InvShiftRows; InvSubBytes; MixColumns; Rijndael advanced encryption standard; ShiftRows; SubBytes; area cost reduction; area reduction; bit-level minimization; bit-level substitution; cipher process; decipher process; standard implementation; Arithmetic; Computer science; Cost function; Cryptography; Minimization methods; Optimization methods; Performance analysis; Scalability; Table lookup; US Government;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2004. Proceedings. The 2004 IEEE Asia-Pacific Conference on

Conference_Location

Tainan

Print_ISBN

0-7803-8660-4

Type

conf

DOI

10.1109/APCCAS.2004.1412768

Filename

1412768