Two efficient area reduction methods for implementations of the Rijndael advanced encryption standard

In this paper, we propose two methods to reduce the area cost of AES chip. The first method combines the SubBytes(), ShiftRows() and MixColumns() transformations in the cipher process, and the InvMixColumns(), InvShiftRows() and InvSubBytes() in the decipher process through the bit-level substitution and minimization. The second method integrates the combined SubBytes()/ShiftRows()/MixColumns() with the InvMixColumns()/InvShiftRows()/InvSubBytes() into a single function unit by sharing the common operations. Experimental results show that our design saves 21 % area cost of the entire AES chip