A variable-length DHT-based FFT/IFFT processor for VDSL/ADSL systems

Author

Pao, Tsung-Chieh ; Chang, Ching-Chi ; Wang, Chomg-Kuang

Author_Institution

Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei

Volume

1

fYear

2004

fDate

6-9 Dec. 2004

Firstpage

381

Abstract

In this paper, a matrix form of the radix-4 Discrete Hartly Transform (DHT) algorithm is derived. And two process element (PE) circuits are proposed for the variable-length application. One is for radix-2 with one real multiplier and three adders, and the other is for radix-4 with one real multiplier and seven adders. The radix-4 DHT processor of variable-length, namely, 8192/4096/2048/1024/512, meets the DMT-VDSL and ADSL requirements. Only six real multipliers, 2.01 N (16467) registers and simple logic circuits are used to perform 8192-points FFT/IFFT in 23 mus. Implemented in 0.25mum 1P5M typical CMOS technology, the core occupies an active area of 5mm times 5mm. Power dissipation is 300mW using a 2.5V supply voltage

Keywords

CMOS logic circuits; adders; digital subscriber lines; fast Fourier transforms; multiplying circuits; signal processing; 0.25 micron; 2.5 V; 23 mus; 300 mW; ADSL; CMOS technology; DHT processor; DMT-VDSL; FFT/IFFT processor; adders; discrete Hartly transform; logic circuits; multiplier; power dissipation; process element circuits; radix-2; radix-4; variable-length application; Adders; Circuits; Councils; DH-HEMTs; Equations; Frequency; Matrix decomposition;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2004. Proceedings. The 2004 IEEE Asia-Pacific Conference on

Conference_Location

Tainan

Print_ISBN

0-7803-8660-4

Type

conf

DOI

10.1109/APCCAS.2004.1412775

Filename

1412775