A low jitter phase-lock loop based on a new adaptive bandwidth controller

Author

Hur, Chel ; Choi, YoungShig ; Choi, HyekHwan ; Kwon, TaeHa

Author_Institution

Div. of Electron., Comput. & Telecommun. Eng., Pukyong Nat. Univ., Pusan

Volume

1

fYear

2004

fDate

6-9 Dec. 2004

Firstpage

421

Abstract

This paper presents the analog adaptive phase-locked loop (PLL) architecture with a new adaptive bandwidth controller to reduce locking time and minimize jitter in PLL output for wireless communication. It adaptively controls the loop bandwidth according to the locking status. The adaptive bandwidth control is implemented by controlling charge pump current depending on the locking status. It is simulated by HSPICE and achieves the primary reference sidebands at the output of the VCO at approximately -80dBc

Keywords

SPICE; bandwidth allocation; jitter; phase locked loops; voltage-controlled oscillators; HSPICE; VCO; adaptive bandwidth controller; charge pump current; jitter; locking time; loop bandwidth; phase-lock loop; primary reference sidebands; wireless communication; Adaptive control; Bandwidth; Charge pumps; Circuits; Communication system control; Jitter; Phase locked loops; Programmable control; Voltage-controlled oscillators; Wireless communication;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2004. Proceedings. The 2004 IEEE Asia-Pacific Conference on

Conference_Location

Tainan

Print_ISBN

0-7803-8660-4

Type

conf

DOI

10.1109/APCCAS.2004.1412785

Filename

1412785