• DocumentCode
    430711
  • Title

    A new dynamic scaling FFT processor

  • Author

    Lin, Yu-Wei ; Lee, Chen-Yi

  • Author_Institution
    Dept. of Electron. Eng., Nat. Chiao Thung Univ., HsinChu, Taiwan
  • Volume
    1
  • fYear
    2004
  • fDate
    6-9 Dec. 2004
  • Firstpage
    449
  • Abstract
    A new FFT processor with radix-8 algorithm and novel matrix buffer is presented in this paper. About 64 K bit memory can be saved in 8 K-point FFT by new dynamic scaling approach. Moreover, with data scheduling and pre-fetched buffering, single-port memory can be adopted in our FFT processor. A test chip for 8 K mode DVB-T system has been designed and fabricated using 0.18 μm CMOS process with core area of 4.84 mm2 and consumes only 25.2 mW at 20 MHz.
  • Keywords
    CMOS memory circuits; buffer circuits; digital arithmetic; fast Fourier transforms; 20 MHz; 25.2 mW; CMOS process; FFT processor; data scheduling; dynamic scaling approach; fast Fourier transforms; matrix buffer; pre-fetched buffering; radix-8 algorithm; single-port memory; CMOS process; Digital video broadcasting; Processor scheduling; System testing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems, 2004. Proceedings. The 2004 IEEE Asia-Pacific Conference on
  • Print_ISBN
    0-7803-8660-4
  • Type

    conf

  • DOI
    10.1109/APCCAS.2004.1412793
  • Filename
    1412793
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=430711