Register-constrained inclusion scheduling for imprecise specification

This paper proposes a scheduling algorithm which considers imprecise system characteristics and constraints. We create a model to model the imprecise latency characteristic as well as imprecise register usage based on fuzzy sets. Given a set of functional units, the proposed algorithm attempts to create a schedule which minimizes the latency and register usage, maximizing overall satisfiability. The experiments show that we can achieve an acceptable schedule with up to 30% saving of number of registers compared to the original algorithm.