DocumentCode
431028
Title
An approach to unified phase compiler by use of 3D representation space
Author
Miyoshi, Takefumi ; Sugino, Nobuhiko
Author_Institution
Dept. of Adv. Appl. Electron., Tokyo Inst. of Technol., Japan
Volume
B
fYear
2004
fDate
21-24 Nov. 2004
Firstpage
349
Abstract
A novel unified phase compiler framework for embedded VLIWs and DSPs is shown. In this compiler, a given program is represented in 3D representation space, which enables to estimate required resources and elapsed time quantatively. Transformation of 3D representation graph which corresponds to an optimization method for specific processor architecture is also proposed. The proposal compiler and the optimization methods are compared with ordinary compiler in terms of their generated codes, and hence they are proved to be effective.
Keywords
digital signal processing chips; embedded systems; optimising compilers; parallel architectures; 3D representation space; DSP; embedded VLIW; optimization method; unified phase compiler; Digital signal processing; Optimization methods; Program processors; Proposals;
fLanguage
English
Publisher
ieee
Conference_Titel
TENCON 2004. 2004 IEEE Region 10 Conference
Print_ISBN
0-7803-8560-8
Type
conf
DOI
10.1109/TENCON.2004.1414603
Filename
1414603
Link To Document