An approach to unified phase compiler by use of 3D representation space

A novel unified phase compiler framework for embedded VLIWs and DSPs is shown. In this compiler, a given program is represented in 3D representation space, which enables to estimate required resources and elapsed time quantatively. Transformation of 3D representation graph which corresponds to an optimization method for specific processor architecture is also proposed. The proposal compiler and the optimization methods are compared with ordinary compiler in terms of their generated codes, and hence they are proved to be effective.