DocumentCode
431117
Title
VLSI architecture for Rayleigh and Rician fading generators
Author
Rao, G. Narasimha ; Bhattacharjee, Ratnajit ; Nandi, Sukumar
Author_Institution
Indian Inst. of Technol., Guwahati, India
Volume
C
fYear
2004
fDate
21-24 Nov. 2004
Firstpage
121
Abstract
In this paper, an architecture suitable for the VLSI implementation of mobile wireless communication channel (Rayleigh and Rician) emulator has been developed and its performance has been evaluated on FPGA platform. The emulator is based on mathematical model proposed by Xiao and Zheng for Rayleigh and Rician fading channels. The proposed design models the mathematical model so as to make it suitable for VLSI implementation. The results obtained from the proposed FPGA implementation have been found satisfactory.
Keywords
Rayleigh channels; Rician channels; VLSI; field programmable gate arrays; mobile radio; FPGA platform; Rayleigh fading generators; Rician fading generators; VLSI architecture; mathematical model; mobile wireless communication channel; Circuit simulation; Fading; Field programmable gate arrays; Mathematical model; Oscillators; Rayleigh channels; Rician channels; Statistics; Very large scale integration; Wireless communication;
fLanguage
English
Publisher
ieee
Conference_Titel
TENCON 2004. 2004 IEEE Region 10 Conference
Print_ISBN
0-7803-8560-8
Type
conf
DOI
10.1109/TENCON.2004.1414722
Filename
1414722
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