• DocumentCode
    431122
  • Title

    A new DCPLL with low jitter based on double-edge mode

  • Author

    Sasaki, Hirofumi ; Fujimoto, Kuniaki ; Yahara, Mitsutoshi

  • Author_Institution
    Sch. of Eng., Kyushu Tokai Univ., Kumamoto, Japan
  • Volume
    C
  • fYear
    2004
  • fDate
    21-24 Nov. 2004
  • Firstpage
    141
  • Abstract
    In this paper, we propose a new DCPLL (dividing ratio changeable all digital phase locked loop) with controllable dividing ratio. In a steady state, the output jitter of this circuit always becomes less than half-period of the fixed clock. Also, using selector instead of the double-edge counter can reduce the circuit scale of the proposed DCPLL.
  • Keywords
    digital communication; digital phase locked loops; jitter; PLL; digital communication; digital phase locked loop; double-edge mode; jitter; Clocks; Counting circuits; Digital communication; Educational institutions; Frequency; Jitter; Laser mode locking; Phase locked loops; Steady-state; Timing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    TENCON 2004. 2004 IEEE Region 10 Conference
  • Print_ISBN
    0-7803-8560-8
  • Type

    conf

  • DOI
    10.1109/TENCON.2004.1414727
  • Filename
    1414727
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=431122