Minimum hardware implementation of multipliers of the lifting wavelet transform

The lifting structured wavelet transform (lifting wavelet) attracts researchers´ attention as a key technology to a lossless and lossy unified coding system of digital image data. For VLSI circuit implementation, multiplier coefficients in the transform must be truncated into finite word length binary values. This report investigates how to appropriately assign error tolerance to each coefficient considering its sensitivity to a typical image signal under a given tolerable total hardware cost. As a result, it is confirmed that the total hardware scale of the multipliers is reduced to 51%.