DocumentCode :
433398
Title :
Multiple-valued VLSI architecture for intra-chip packet data transfer
Author :
Hasegawa, Tomoaki ; Homma, Yuya ; Kameyama, Michitaka
Author_Institution :
Graduate Sch. of Inf. Sci., Tohoku Univ., Sendai, Japan
fYear :
2005
fDate :
19-21 May 2005
Firstpage :
114
Lastpage :
119
Abstract :
A packet data transfer scheme is introduced for intra-chip data transfer to solve an interconnection problem. A protocol suitable for intra-chip data transfer is proposed to make a router as simple as possible. The total number of packets in a micronetwork can be reduced by multiplexing two binary packets into a single multiple-valued packet, which makes the micronetwork throughput very high. The multiplexing can be realized by liner summation of two packets in current-mode logic. Moreover, multiple-valued source-coupled logic is introduced in the router circuit. Thus, we can design the very high-speed micronetwork using current-mode multiple-valued logic.
Keywords :
VLSI; multivalued logic; multivalued logic circuits; network routing; packet switching; system-on-chip; SoC interconnection; VLSI architecture; current-mode logic; high-speed micronetwork; intra-chip packet data transfer; multiple-valued packet; multiple-valued source-coupled logic; router circuit; Arithmetic; Degradation; Integrated circuit interconnections; Logic circuits; Logic design; Protocols; System-on-a-chip; Throughput; Transmission lines; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Multiple-Valued Logic, 2005. Proceedings. 35th International Symposium on
ISSN :
0195-623X
Print_ISBN :
0-7695-2336-6
Type :
conf
DOI :
10.1109/ISMVL.2005.31
Filename :
1423171
Link To Document :
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