• DocumentCode
    433515
  • Title

    An improved estimation methodology for hybrid BIST cost calculation

  • Author

    Jervan, G. ; Zebo Peng ; Ubar, R. ; Korelina, O.

  • Author_Institution
    Linkoping University, Embedded Systems Laboratory
  • fYear
    2004
  • fDate
    8-9 Nov. 2004
  • Firstpage
    297
  • Lastpage
    300
  • Abstract
    This paper presents an improved estimation methodology for hybrid BIST cost calculation. In a hybrid BIST approach the test set is assembled from pseudorandom and deterministic test patterns. The efficiency of the hybrid BIST approach is largely determined by the ratio of those test patterns in the final test set. Unfortunately exact algorithms for finding the test sets are computationally very expensive. Therefore in this paper we propose an improved estimation methodology for fast calculation of the hybrid test set. The methodology is based on real fault simulation results and experimental results have shown that the method is more accurate than the statistical method proposed earlier.
  • Keywords
    Automatic testing; Built-in self-test; Costs; Embedded system; Hybrid power systems; Laboratories; Logic testing; Software testing; System testing; Test pattern generators;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Norchip Conference, 2004. Proceedings
  • Conference_Location
    Oslo, Norway
  • Print_ISBN
    0-7803-8510-1
  • Type

    conf

  • DOI
    10.1109/NORCHP.2004.1423882
  • Filename
    1423882