• DocumentCode
    4337
  • Title

    Random Dopant Fluctuation Induced Variability in Undoped Channel Si Gate all Around Nanowire n-MOSFET

  • Author

    Nayak, Kaushik ; Agarwal, Sankalp ; Bajaj, Mohit ; Murali, Kota V. R. M. ; Rao, Valipe Ramgopal

  • Author_Institution
    Dept. of Electr. Eng., IIT Bombay, Mumbai, India
  • Volume
    62
  • Issue
    2
  • fYear
    2015
  • fDate
    Feb. 2015
  • Firstpage
    685
  • Lastpage
    688
  • Abstract
    In this brief, the random dopant fluctuation (RDF)-induced threshold voltage (VT) variability, ON current (ION) variability, and VT mismatch in undoped channel Si gate-all-around (GAA) n-nanowire MOSFETs (n-NWFETs) are studied using coupled 3-D statistical device simulations considering quantum corrected room temperature drift-diffusion transport. The RDFs are introduced in the Si NWFET tetrahedral device grid by a 3-D atomistic MonteCarlo technique. The RDF due to discrete random dopants located in the source (S)/drain (D) extension and channel regions of Si GAA n-NWFET are found to impact the device characteristic variability. The numerical VT mismatch analysis and comparison with the Si n-NWFET total AVT measurement data from the literature reveal that RDF still plays a significant source for device random fluctuations in undoped channel Si GAA n-NWFETs. The numerical VT mismatch study indicates the fact that complete suppression of RDF induced device random variability in undoped channel fully depleted MOS devices is still going to be a challenge, as long as doped S/D regions are employed.
  • Keywords
    MOSFET; Monte Carlo methods; elemental semiconductors; nanoelectronics; silicon; 3D atomistic Monte-Carlo technique; 3D statistical device simulations; Si; Si NWFET; device characteristic variability; device random variability; discrete random dopants; drift-diffusion transport; fully depleted MOS devices; nanowire n-MOSFET; numerical mismatch analysis; random dopant fluctuation; room temperature; tetrahedral device; threshold voltage variability; undoped channel silicon gate; CMOS integrated circuits; Logic gates; MOSFET; Resource description framework; Semiconductor process modeling; Silicon; Solid modeling; CMOS; Characteristic fluctuations; device performance; gate-all-around (GAA); mismatch; random dopant fluctuations (RDFs); silicon nanowire FET (NWFET); variability; variability.;
  • fLanguage
    English
  • Journal_Title
    Electron Devices, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9383
  • Type

    jour

  • DOI
    10.1109/TED.2014.2383352
  • Filename
    7001667