DocumentCode
4350
Title
Backend Dielectric Reliability Full Chip Simulator
Author
Bashir, Muhammad M. ; Chang-Chih Chen ; Milor, Linda ; Dae Hyun Kim ; Sung Kyu Lim
Author_Institution
Sch. of Electr. & Comput. Eng., Georgia Tech, Atlanta, GA, USA
Volume
22
Issue
8
fYear
2014
fDate
Aug. 2014
Firstpage
1750
Lastpage
1762
Abstract
Backend dielectric breakdown degrades the reliability of circuits. A methodology to estimate chip lifetime because of backend dielectric breakdown is presented. It incorporates failures because of parallel tracks, the width effect, and field enhancement due to line ends. It also includes the operating temperature and activity.
Keywords
electric breakdown; failure analysis; integrated circuit reliability; backend dielectric breakdown; backend dielectric reliability full chip simulator; chip lifetime; circuit reliability; failures; field enhancement; line ends; operating temperature; parallel tracks; width effect; Dielectric breakdown; Dielectrics; Feature extraction; Geometry; Layout; Reliability; Weibull distribution; Design for manufacture; dielectric breakdown; integrated circuit reliability; integrated circuit reliability.;
fLanguage
English
Journal_Title
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
Publisher
ieee
ISSN
1063-8210
Type
jour
DOI
10.1109/TVLSI.2013.2277856
Filename
6595154
Link To Document