Global false path-aware hierarchical timing analysis

As the integrated technology develops we can design the circuit with thousands of transistors. A hierarchical design Is unavoidable because of a huge circuit size. It is more important how we can consider hierarchically meaningful structure in circuit delay analysis. We computed more accurately the delay of circuit by adding the notation global false path to a previous hierarchical timing analysis. This paper presents the hierarchical timing analysis approach using functional relations considering global false path. Our algorithm utilizes the global false path, the functional relations between the modules. Therefore, the more accurate circuit delay can be obtained than the previous approach. Our algorithm is applied to ISCAS´85 benchmark circuits and carry skip adder. Our experimental results verify that the proposed algorithm is very effective for calculating the circuit delay.