Optimizing low-power high-speed full adders with simulated annealing

Author

Amirabadi, Amir ; Mortazavi, Yadollah ; Afzali-Kusha, Ali

Author_Institution

Dept. of Electr. & Comput. Eng., Tehran Univ., Iran

fYear

2004

fDate

6-8 Dec. 2004

Firstpage

429

Lastpage

432

Abstract

In this paper, a random search algorithm known as simulated annealing (SA) has been employed to optimize the sizing of a number of digital adder circuits. The SA algorithm is implemented in MATLAB; the cost function, a function of power and delay, is accurately computed using HSPICE for a 0.35 μm technology. Using a piecewise linear and logarithmic cost function, the delay and power is optimized in an intelligent fashion. The results show a 60% reduction in power and a 65% reduction in delay with respect to previous designs based on analytical calculations.

Keywords

SPICE; adders; circuit optimisation; digital integrated circuits; digital simulation; high-speed integrated circuits; integrated circuit design; logic design; low-power electronics; piecewise linear techniques; simulated annealing; 0.35 micron; HSPICE; MATLAB; digital adder circuits; digital integrated circuits; logarithmic cost function; logic design; low power high speed full adders; piecewise linear function; random search algorithm; simulated annealing algorithm; Adders; Circuit simulation; Computational modeling; Cost function; Delay; Design engineering; MATLAB; Optical computing; Piecewise linear techniques; Simulated annealing;

fLanguage

English

Publisher

ieee

Conference_Titel

Microelectronics, 2004. ICM 2004 Proceedings. The 16th International Conference on

Print_ISBN

0-7803-8656-6

Type

conf

DOI

10.1109/ICM.2004.1434605

Filename

1434605