VLSI implementation of a floating-point divider

In this paper, we present the VLSI implementation of a low power floating-point divider in CMOS 0.18 μm technology using radix-2 over redundant number system. This divider implementation is well suited for IEEE 754 floating point standard and can be widely used in DSP applications. In the proposed divider designs, different PPM adders, based on 24, 22 and new 16-transistor circuits are used to implement the carry-free addition/subtraction unit. Different designs of quotient selection logic and reducing unit are also presented. Then, these designs are compared for power dissipation, time delay, and area. Our new design of a 4-bit divider has 9% less EDP and 17% less area than previous work.