DocumentCode :
435682
Title :
Platform and architecture adequacy in SoC environment: a case study
Author :
Aoudni, Y. ; Amor, N.B. ; Gogniat, G. ; Philippe, J.L. ; Abid, M.
Author_Institution :
LESTER Lab., Univ. de Bretagne Sud, Lorient, France
fYear :
2004
fDate :
6-8 Dec. 2004
Firstpage :
762
Lastpage :
767
Abstract :
This work aims to compare several tools and SoC platforms according to the following key parameters: FPGA architecture, coprocessor and accelerator integration, RTOS and HW-SW refinement tools. These key parameters are required to select a flexible and efficient SoC platform (and the associated tools) in order to implement an efficient PACM (processor-accelerator-coprocessor-memory) architecture model. A case study for the PACM architecture model has been targeted in order to validate proposed key parameters. Four platforms were candidate to implement the PACM architecture model. Finally, a Nios development kit (Quartus, SOPC builder and STRATIX device) is used as a prototyping platform for PACM architecture and a shading algorithm for 3D image treatment was implemented as an application to prove the SoC platform adequacy with our PACM architecture model.
Keywords :
coprocessors; field programmable gate arrays; hardware-software codesign; integrated circuit design; system-on-chip; 3D image treatment; FPGA architecture; HW-SW refinement tool; Nios development kit; Quartus development kit; SOPC builder; STRATIX device; SoC environment; processor-accelerator-coprocessor-memory architecture; real time operating systems; shading algorithm; Application software; Computer aided software engineering; Computer architecture; Coprocessors; Educational institutions; Hardware; Memory architecture; Prototypes; Signal processing algorithms; Software performance;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Microelectronics, 2004. ICM 2004 Proceedings. The 16th International Conference on
Print_ISBN :
0-7803-8656-6
Type :
conf
DOI :
10.1109/ICM.2004.1434778
Filename :
1434778
Link To Document :
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