• DocumentCode
    435694
  • Title

    Impact of metal gate work function on nano CMOS device performance

  • Author

    Hou, Y.T. ; Low, Tony ; Xu, Bin ; Li, Ming-Fu ; Samudra, G. ; Kwong, D.L.

  • Author_Institution
    Dept. Electr. & Comput. Eng., Nat. Univ. of Singapore, Singapore
  • Volume
    1
  • fYear
    2004
  • fDate
    18-21 Oct. 2004
  • Firstpage
    57
  • Abstract
    We studied two effects in the metal gate work function engineering in nano CMOSFETs: (1) Gate work function shifts induced by carrier quantization in Si and Ge ultra-thin body FETs with sub-10 nm body thickness and different surface orientations. Guidelines for metal gate work function engineering are provided and technical challenges identified; (2) we presented a systematic study on gate tunneling characteristics of metal gate CMOSFETs. A reduction of gate to source/drain extension tunneling is found when using near mid-gap metal gate in SOI CMOS, especially when using high-K dielectric. Benefits of this reduction to transistor off-state leakage and to future CMOS scaling were analyzed.
  • Keywords
    CMOS integrated circuits; MOSFET; nanoelectronics; silicon-on-insulator; tunnelling; work function; CMOS scaling; SOI CMOS; body thickness; carrier quantization; gate tunneling characteristics; high-K dielectric; metal gate CMOSFET; metal gate work function; nano CMOS device performance; source/drain extension tunneling; surface orientations; transistor off-state leakage; ultra-thin body FET; CMOSFETs; Dielectric materials; FETs; High K dielectric materials; High-K gate dielectrics; MOS devices; Microelectronics; Quantization; Tunneling; USA Councils;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State and Integrated Circuits Technology, 2004. Proceedings. 7th International Conference on
  • Print_ISBN
    0-7803-8511-X
  • Type

    conf

  • DOI
    10.1109/ICSICT.2004.1434953
  • Filename
    1434953