A novel asymmetric graded low doped drain (AGLDD) vertical channel nMOSFET with sidewall masked (SWAM) LOCOS isolation

Vertical channel nMOSFET with asymmetric graded low doped drain (AGLDD) structure and sidewall masked (SWAM) LOCOS isolation process is first investigated and experimentally demonstrated. The AGLDD structure, which is formed by conventional ion implantation and impurity diffusion, is adopted to suppress short channel effects and hot carrier effect. The SWAM LOCOS isolation is used to eliminate the parasitic polysilicon sidewall gate capacitances around the active region edge. The fabrication process of this device is compatible with planar CMOS technology. The transistors show veiy good immunity of short channel effects in DC characteristics.