Spacer design between source/drain and gate for high-performance FinFET devices

As the gate length is scaling down, the spacer design for FinFET becomes increasingly important especially for high performance. In this paper, the triangle spacer is proposed to replace the conventional rectangle spacer and the results demonstrate that for FinFET with 14-nm gate length, with the triangle spacer, the drive current can be increased by about 67% relative to the conventional rectangle spacer. The parasitic gate capacitance also increases due to the introduction of triangle spacer. The gate delay is calculated and the results show that with the triangle spacer, the delay can be reduced by about 33% due to the increased drive current relative to the rectangle spacer.