Structure evolution in ULSI interconnects toward 65nm/45nm-nodes ASICs

Due to abrupt increment of the interconnect length in the 65nm-node ASICs, the total interconnect parasitic capacitance is not ignored relative to the total transistor capacitance on the chip. Therefore, by replacement of the conventional SiO₂ interlayer dielectric (ILD, k=4.2) film to a porous low-k film (k=2.5) in 65nm-nodes, the chip performance such as "multi-functionality and low-power consumption" is estimated to achieve 20-40% improvement. From a view point of the chip fabrication, however, the porous low-k films have difficulties in process integration due to their mechanical and electrical weaknesses. The pore size control in sub-nanometer scales and the pore scaling at the side-walls of line trenches and vias are key technologies to improve the interconnect reliability. For 45nm-node ASICs and beyond, molecular-level controls in the pore structure and the chemical composition of ultra low-k, porous films will be needed to keep the interconnect reliability.