DocumentCode :
435775
Title :
Structure evolution in ULSI interconnects toward 65nm/45nm-nodes ASICs
Author :
Hayashi, Yoshihiro
Author_Institution :
Syst. Devices Res. Labs., NEC Corp., Sagamihara, Japan
Volume :
1
fYear :
2004
fDate :
18-21 Oct. 2004
Firstpage :
480
Abstract :
Due to abrupt increment of the interconnect length in the 65nm-node ASICs, the total interconnect parasitic capacitance is not ignored relative to the total transistor capacitance on the chip. Therefore, by replacement of the conventional SiO2 interlayer dielectric (ILD, k=4.2) film to a porous low-k film (k=2.5) in 65nm-nodes, the chip performance such as "multi-functionality and low-power consumption" is estimated to achieve 20-40% improvement. From a view point of the chip fabrication, however, the porous low-k films have difficulties in process integration due to their mechanical and electrical weaknesses. The pore size control in sub-nanometer scales and the pore scaling at the side-walls of line trenches and vias are key technologies to improve the interconnect reliability. For 45nm-node ASICs and beyond, molecular-level controls in the pore structure and the chemical composition of ultra low-k, porous films will be needed to keep the interconnect reliability.
Keywords :
ULSI; application specific integrated circuits; dielectric thin films; integrated circuit interconnections; nanotechnology; 45 nm; 45nm-node ASIC; 65 nm; 65nm-node ASIC; SiO2; SiO2 interlayer dielectric film; ULSI interconnects; chemical composition; electrical weakness; interconnect parasitic capacitance; interconnect reliability; line trench side walls; mechanical weakness; molecular-level control; pore scaling; pore size control; pore structure; porous low-k film; process integration; sub-nanometer scale; transistor capacitance; ultra low-k porous film; Application specific integrated circuits; Chemicals; Chip scale packaging; Dielectric films; Energy consumption; Integrated circuit interconnections; Parasitic capacitance; Size control; Transistors; Ultra large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Solid-State and Integrated Circuits Technology, 2004. Proceedings. 7th International Conference on
Print_ISBN :
0-7803-8511-X
Type :
conf
DOI :
10.1109/ICSICT.2004.1435052
Filename :
1435052
Link To Document :
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