Scaling of shallow trench isolation with stress control for 65nm node and beyond

A progressive scaling of both intra- and inter-well isolation has been carried out for SoC (system on chip) with 65nm technology node and beyond, resulting in increased chip speed, increased transistor density, and lower cost performance. Shallow trench isolation (STI) with almost no encroachment, good planarity, higher isolation property, is a most promising isolation scheme for ULSI application (Faza et al., 1993; Bryant et al., 1994; Nandakumar et al., 1998). However, this rapid scaling of STI needs several difficult challenges from the viewpoints of both the process technology and the device property. In this paper, the major issues for STI scaling are described and some solutions are discussed to overcome the scaling crisis.