Nanoscale silicon-oxide-nitride-oxide-silicon (SONOS) structure and its applications

We present nanoscale 2-bit SONOS flash memories with a merged-triple damascene gate structure by using inverted sidewall patterning technique, which separates the charge storage nodes physically. As a result, we have solved the problems of the charge redistribution and diffusion in the nitride layer which plague the conventional 2-bit SONOS devices (i.e. NROMs) in the nanoscale regime. The new cell structures have shown better 2-bit operation (P/E) and excellent reliability characteristics in the 90-nm channel regime. We have also turned the 2-bit SONOS memory into a novel MOSFET structure with programmable virtual source/drain (PVS) for LOP and LSTP MOSFET operations. PVS MOSFETs with charged-nitride nodes for virtual source/drain formation show a small drain leakage and well-controlled short channel effect which are indispensable for low operating power (LOP) and low stand-by power (LSTP) applications.