Title :
A design based yield and redundancy model for high density dualport SRAM on 90nm technology
Author :
Peng, Tao ; Landry, Greg ; Iandolo, Walter
Author_Institution :
New England Design Center, Cypress Semicond., Nashua, NH, USA
Abstract :
A design based yield and redundancy model for high density dual port SRAM on 90nm technology was presented in this paper. The memory array bitmap and repairability were analyzed from both layout and circuit architecture perspective. The fault signature was categorized by repairing method. The proposed modeling approach allowed direct correlation between circuit architecture and redundancy design thus improved the repair efficiency. The model proved to be valuable for DFY (design for yield) and guided process improvement for yield.
Keywords :
SRAM chips; design for manufacture; integrated circuit layout; integrated circuit yield; nanotechnology; redundancy; 90 nm; circuit architecture; circuit layout; design for yield; fault signature; high density dualport SRAM; memory array bitmap; process improvement; redundancy design; redundancy model; repair efficiency; repairing method; Area measurement; Circuit analysis; Circuit faults; Failure analysis; Manufacturing; Paper technology; Random access memory; Redundancy; Silicon; Usability;
Conference_Titel :
Solid-State and Integrated Circuits Technology, 2004. Proceedings. 7th International Conference on
Print_ISBN :
0-7803-8511-X
DOI :
10.1109/ICSICT.2004.1435106
