Title :
Design and modeling of tapered LWL architecture for high density SRAM
Author :
Wong, Robert ; Peng, Tao ; Landry, Greg
Author_Institution :
Cypress Semicond. NEDC, Nashua, NH, USA
Abstract :
Tapered local word line driver architecture is proposed for high density SRAM design. The tapered circuit observed a 7% speed improvement. An analytical model is presented for fast simulation and gate size optimization.
Keywords :
SRAM chips; integrated circuit design; integrated circuit modelling; memory architecture; analytical model; gate size optimization; high density SRAM; speed improvement; tapered LWL architecture; tapered circuit; tapered local word line driver; Analytical models; Capacitance; Circuit simulation; Delay; OWL; Pulse inverters; Random access memory; Signal design; Tiles; Wire;
Conference_Titel :
Solid-State and Integrated Circuits Technology, 2004. Proceedings. 7th International Conference on
Print_ISBN :
0-7803-8511-X
DOI :
10.1109/ICSICT.2004.1435107
