Compacted simulation: a new leakage current estimation method

Leakage current of CMOS circuit is increasing dramatically with the technology scales and emerging as a critical issue of high performance system. Subthreshold, gate and reverse biased junction band-to-band tunneling (BTBT) leakage are considered as the three main sources of the total leakage current. Up to now, how to estimate leakage current of large-scale circuits accurately within endurable runtime remains unsolved, although accurate leakage models have been broadly discussed. In this paper, a new method called compacted simulation for leakage current estimation is proposed. We set up experimental flows of three other popular methods for validation and the results show the method achieves very good accuracy (under 0.5%) with several orders of speedup compared with leakage current simulation at circuit level.