Title :
Test scheduling for core-based SOCs
Author :
Guang, Zhang Yong ; Xin, Xu Yuan ; Bin, Dong ; Kuang, Wang
Author_Institution :
Inst. of Inf. & Commun. Eng., Zhejiang Univ., Hangzhou, China
Abstract :
In this paper, the modeling of system-on-a-chip (SOC) test optimization has been formulated with different precedence, resource and core constraints. A neural network combined with heuristic algorithm has been developed to solve the large size SOC test problems. As demonstrated by the results that computer implement the developed method can not only solve the large size SOC test problems, but is also capable of finding the optimal solutions within reasonable computing time.
Keywords :
circuit optimisation; integrated circuit modelling; integrated circuit testing; neural nets; system-on-chip; SOC test optimization; core-based SOC; heuristic algorithm; neural network; system-on-a-chip; test scheduling; Constraint optimization; Enterprise resource planning; Intellectual property; Job shop scheduling; Logic testing; Neural networks; Process design; Silicon; System testing; System-on-a-chip;
Conference_Titel :
Solid-State and Integrated Circuits Technology, 2004. Proceedings. 7th International Conference on
Print_ISBN :
0-7803-8511-X
DOI :
10.1109/ICSICT.2004.1436830
