Title :
A 3.125Gbit/s CMOS clock and data recovery circuit
Author :
Gan, Guo ; Lin, Huang ; Jinghua, Ye ; Yihui, Chen ; Hong Zhiliang
Author_Institution :
ASIC & Syst. State Key Lab., Fudan Univ., Shanghai, China
Abstract :
A 3.125Gbit/s clock and data recovery (CDR) circuit is described. The circuit adopts parallel structure to recover clock from high-speed data stream. The working clock is reduced by this method and lower power is achieved. Timing jitter has been considered carefully and the loop parameters are optimized to reduce the output jitter. The circuit is designed with 0.18μm CMOS process: the simulated function and performance meet the requirements and the core power dissipation is 56mW.
Keywords :
CMOS digital integrated circuits; clocks; timing jitter; 0.18 micron; 3.125 Gbit/s; 56 mW; CMOS clock data recovery circuit; data stream; loop parameter; parallel structure; power dissipation; timing jitter; Bandwidth; CMOS process; Circuits; Clocks; Ethernet networks; Frequency; Gallium nitride; Jitter; Phase locked loops; Voltage-controlled oscillators;
Conference_Titel :
Solid-State and Integrated Circuits Technology, 2004. Proceedings. 7th International Conference on
Print_ISBN :
0-7803-8511-X
DOI :
10.1109/ICSICT.2004.1436857
