A dual complex pole-zero cancellation compensation mode for three-stage amplifier

A new dual complex pole-zero cancellation (DCPC) frequency compensation mode is proposed in this paper. It uses one pair of complex zeros to cancel one pair of complex poles, resulting in the feature that the frequency response of the three-stage amplifier exhibits that of a one-pole system. Thus the bandwidth is expected to be increased several times compared to conventional approaches. Moreover, this technique requires only one very small compensation capacitor even when driving a large load capacitor. A GBW of 4.6 MHz, DC gain of 100 dB, PM of 89.2° and power dissipation of 0.87 mW can be achieved for a load capacitor of 100 pF with a single Miller compensation capacitor of 2 pF at a ±1V supply in a standard 0.6-μm CMOS technology.