A stack-mode low power prescaler in ISM band ASK receiver

Author

Hong, Liang ; Xu, Yongsheng ; Lai, Zongsheng

Author_Institution

Inst. of Microelectron. Circuits & Syst., East China Normal Univ., Shanghai, China

Volume

2

fYear

2004

fDate

18-21 Oct. 2004

Firstpage

1516

Abstract

This paper presents a divide-by-64 low power prescaler operating up to GHz frequency. By adopting the stacked structure circuits, the power consumption of the prescaler has been reduced to 3.8mW (@5v power supply, 1.2GHz). Moreover, the layout area is also reduced to 0.47mm² through this structure. In this paper, this circuit is applied in the PLL of an ASK receiver which operates at ISM band from 290MHz to 460MHz. Simulated with Hspice and Cadence Spectre, the circuit is implemented at a 0 8μm BiCMOS process.

Keywords

BiCMOS digital integrated circuits; amplitude shift keying; integrated circuit layout; low-power electronics; phase locked loops; prescalers; radio receivers; 0.8 micron; 1.2 GHz; 290 to 460 MHz; 3.83 mW; 5 V; ASK receiver; BiCMOS process; Cadence Spectre; Hspice; ISM band; amplitude shift keying; circuit simulation; phase locked loop; stack-mode low power prescaler; stacked structure circuit; Amplitude shift keying; Circuit simulation; Energy consumption; Flip-flops; Frequency conversion; Latches; Phase locked loops; Power supplies; Radiofrequency integrated circuits; Voltage-controlled oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State and Integrated Circuits Technology, 2004. Proceedings. 7th International Conference on

Print_ISBN

0-7803-8511-X

Type

conf

DOI

10.1109/ICSICT.2004.1436900

Filename

1436900