An optimized architecture for implementing image convolution with reconfigurable hardware

Convolution is a very important operation within computer vision. It can he characterized as being computationally intensive, so it Is hard to implement real-time convolution. One reason for this is the vast amount of data that requires processing (more than nine million pixels per second for typical image sources). This paper introduces a new architecture along with its optimizations for implementing convolution in FPGAs. The proposed architecture uses techniques of parallelism with some improvements. The system uses a HOTZ-XL board, and we have developed a Visual C++ application to validate our hardware designs. This environment is based on a library of hardware modules implementing the most common operations in image processing. In this paper we focus on the convolution modules. The results illustrate the effectiveness of our improvements allowing real-time processing, a minimum resource use and high operation frequency.