• DocumentCode
    43622
  • Title

    Bilayer Graphene-Hexagonal Boron Nitride Heterostructure Negative Differential Resistance Interlayer Tunnel FET

  • Author

    Sangwoo Kang ; Fallahazad, Babak ; Kayoung Lee ; Movva, Hema ; Kyounghwan Kim ; Corbet, Chris M. ; Taniguchi, Takashi ; Watanabe, Kenji ; Colombo, Luigi ; Register, Leonard F. ; Tutuc, Emanuel ; Banerjee, Sanjay K.

  • Author_Institution
    Microelectron. Res. Center, Univ. of Texas at Austin, Austin, TX, USA
  • Volume
    36
  • Issue
    4
  • fYear
    2015
  • fDate
    Apr-15
  • Firstpage
    405
  • Lastpage
    407
  • Abstract
    We present the room temperature operation of a vertical tunneling field-effect transistor using a stacked double bilayer graphene (BLG) and hexagonal boron nitride heterostructure. The device shows two tunneling resonances with negative differential resistance (NDR). An analysis of the electrostatic potential drop across the heterostructure indicates the resonances are associated with the relative alignment of the lower or upper bands of the two BLG. Using the NDR characteristic of the device, one-transistor latch or SRAM operation is demonstrated. The device characteristics are largely insensitive to temperature from 1.5 to 300 K.
  • Keywords
    SRAM chips; boron compounds; flip-flops; graphene; high electron mobility transistors; resonant tunnelling transistors; stacking; BLG; BN; C; NDR characteristic; SRAM operation; electrostatic potential drop analysis; hexagonal heterostructure; lower-upper bands; negative differential resistance interlayer tunnel FET; one-transistor latch; relative alignment; room temperature operation; stacked double bilayer graphene; temperature 1.5 K to 300 K; tunneling resonances; vertical tunneling field-effect transistor; Electric potential; Electrostatics; Graphene; Latches; Random access memory; Resonant tunneling devices; Negative differential resistance; bilayer graphene; hexagonal boron nitride; latch; negative differential resistance; resonant tunneling; static random access memory; tunneling field effect transistor;
  • fLanguage
    English
  • Journal_Title
    Electron Device Letters, IEEE
  • Publisher
    ieee
  • ISSN
    0741-3106
  • Type

    jour

  • DOI
    10.1109/LED.2015.2398737
  • Filename
    7027824