A new systolic architecture without global broadcast

In this paper, we propose a new systolic architecture without global broadcast, by using a block-based scheme to eliminate global signals, with a pipelined bus to convex data globally. The control signals and intermediate results are transmitted by shift registers. All signals, except for the clock signal, are limited in one block or between two adjacent blocks. This architecture has local broadcast which contributes to a high operation throughput. Redesigned (4:2) compressors are used in the carry-save-adder structure, which contributes to speed improvement and area saving. Furthermore, we apply the proposed architecture on modular multiplication, which is a main part of some cryptography and signal processing algorithms.