Title :
Quality assurance verification using a virtual prototyping system
Author :
McGarry, L. ; Qu, K.Y. ; Lee, Wei-Jen ; Wilson, T.G.
Author_Institution :
Martin Sun Astec Custom Power (HK) Ltd., Kowloon
Abstract :
The concept of a virtual prototyping system using simulation and IP blocks has been outlined. This paper discusses an extension of the virtual prototyping simulation system by applying those tools and techniques to simulate many of the parameters required to complete a quality assurance verification (QAV) test. These include electrical parameter stress, worst case analysis, component derating, worst case system over stress and impact on MTBF calculations
Keywords :
electronic design automation; industrial property; integrated circuit testing; piecewise linear techniques; quality assurance; virtual prototyping; IP block; MTBF calculation; SIMPLIS; electrical parameter stress; electronic design verification test; intellectual property block; quality assurance verification; simulation for piecewise linear system; virtual prototyping system; Analytical models; Circuit simulation; Circuit testing; Design engineering; Electronic equipment testing; Intellectual property; Quality assurance; Stress; System testing; Virtual prototyping;
Conference_Titel :
Applied Power Electronics Conference and Exposition, 2005. APEC 2005. Twentieth Annual IEEE
Conference_Location :
Austin, TX
Print_ISBN :
0-7803-8975-1
DOI :
10.1109/APEC.2005.1453181
