Performance improvement of hysteresis voltage-controlled forward converters using FPGA-based SR control

Field programmable gate arrays (FPGA) based control of synchronous rectification (SR) is proposed herein and applied to a forward converter with an FPGA-based hysteresis voltage-controlled scheme along with maximum current limiting, without any analogue-to-digital converter (ADC) added. First, methods of approximately estimating the hysteresis band and the output voltage ripple are described. Secondly, an FPGA-based SR control algorithm is developed, and thus the energy fed back from the secondary side to the primary side of the main transformer can make transient load response improved. After this, the procedure for circuit design starts from the current slew rate of the output inductor and the output current slew rate from no to full load. Eventually, the differences in transient load response between with and without the proposed FPGA-based SR control technique are verified via some experimental results.