DocumentCode
43786
Title
SET Tolerance of 65 nm CMOS Majority Voters: A Comparative Study
Author
Danilov, Igor A. ; Gorbunov, Maxim S. ; Antonov, A.A.
Author_Institution
Sci. Res. Inst. of Syst. Anal., Moscow, Russia
Volume
61
Issue
4
fYear
2014
fDate
Aug. 2014
Firstpage
1597
Lastpage
1602
Abstract
We study the design of different majority voters based on a commercial 65 nm CMOS technology, propose the test system and discuss the experimental results of heavy ion irradiation campaign and the proposed relative efficiency criterion for choosing the voter for a given TMR strategy.
Keywords
CMOS logic circuits; integrated circuit reliability; ion beam effects; radiation hardening (electronics); CMOS majority voter; TMR strategy; heavy ion irradiation campaign; relative efficiency criteria; single event transient tolerance; size 65 nm; triple modular redundancy; Arrays; CMOS integrated circuits; Fault tolerance; Fault tolerant systems; Field programmable gate arrays; Transistors; Tunneling magnetoresistance; CMOS; DICE; critical charge; heavy ions; majority voter; single-event transient (SET); triple-modular redundancy (TMR);
fLanguage
English
Journal_Title
Nuclear Science, IEEE Transactions on
Publisher
ieee
ISSN
0018-9499
Type
jour
DOI
10.1109/TNS.2014.2311297
Filename
6827971
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