Title :
Integrated interleaving ECC and high dimensional parity codes
Author :
Kamabe, Hiroshi ; Katou, Hironori
Author_Institution :
Dept. of Information Sci., Gifu Univ., Japan
Abstract :
The integrated interleaving error correcting scheme allows the use of redundancies of different levels through all data blocks. That is, a redundancy of the error correcting capability of a (strong) code can be distributed over data blocks which are encoded with different redundancies. The high dimensional parity code is defined as a product code of simple parity check codes. Since the structure of the code is very simple, expect that the encoding procedure is also simple. Another advantage of the code is that the code can be viewed as a low density parity check code. Therefore the powerful decoding method, the sum-product algorithm can be applied in decoding. In this paper, the codes are used as constituent codes for the integrated interleaving error correcting scheme.
Keywords :
decoding; error correction codes; interleaved codes; parity check codes; data blocks; high dimensional parity codes; integrated interleaving error correcting scheme; product code; simple parity check codes; sum-product algorithm; Decoding; Encoding; Error correction; Error correction codes; Interleaved codes; Linear code; Parity check codes; Product codes; Redundancy; Sum product algorithm;
Conference_Titel :
Magnetics Conference, 2005. INTERMAG Asia 2005. Digests of the IEEE International
Print_ISBN :
0-7803-9009-1
DOI :
10.1109/INTMAG.2005.1463925