Microarchitecture evaluation with floorplanning and interconnect pipelining

As microprocessor technology continues to scale into the nanometer regime, recent studies show that interconnect delay will be a limiting factor for performance, and multiple cycles will be necessary to communicate global signals across the chip. Thus, longer interconnects need to be pipelined, and the impact of the extra latency along wires needs to be considered during early microarchitecture design exploration. In this paper, we address this problem and make the following contributions: (1) a floor plan-driven microarchitecture evaluation methodology considering interconnect pipelining at a given target frequency by selectively optimizing architecture level critical paths; (2) use of microarchitecture performance sensitivity models to weight microarchitectural critical paths during floor planning and optimize them for higher performance; and (3) a methodology to study the impact of frequency scaling on microarchitecture performance with consideration of interconnect pipelining. For a sample microarchitecture design space, we show that considering interconnect pipelining can increase the estimated performance against a no wire pipelining approach between 25% to 45%. We also demonstrate the value of the methodology in exploring the target frequency of the processor.